North American Production Sharing de México, S.A. de C.V.

North American Production Sharing de México, S.A. de C.V.

Administración de maquiladoras.

Giro

Maquiladora (Export.)

Actividad principal

Administración de maquiladoras.

Número de empleados

10000

Sitio Web corporativo

Información

North American Production Sharing (NAPS) assists companies to set up and manage, on an ongoing basis, their own operations in Mexico. Through economies of scale, NAPS is positioned to offer clients excellent personalized service, technological tools to remotely monitor their factories, and full compliance with all the laws of Mexico. Mexico offers an affordable and highly qualified labor force and an ideal location to supply North American markets. Aside from manufacturing operations, NAPS is experienced in establishing BPO, customer support and call centers. NAPS operates primarily in Mexico, in the areas of Tijuana, Mexicali, Ciudad Juarez and throughout the Bajio (Guanajuato) region. NAPS Guanajuato specializes in support services in Japanese for Japan based companies. Specialties: BPO, set-up operations, on-going administration, legal /environmental compliance, remote, secure web-based access to metrics, customs import-export, 24/7 security services in Mexico, Payroll, HR / Benefits Admin, local sourcing of materials / inputs.

171 puestos de Trabajo

Failure Analysis Engineer (Semiconductors)

Required Skills & Qualifications Fast learner with the ability to work independently. Strong understanding of: Semiconductor physics. Device behavior and circuit analysis. Wafer fabrication processes. Proficiency in electrical and physical FA techniques such as: Mechanical polishing, chemical etching. SEM/EDX, curve trace. Thermal emission, photon emission, OBIRCH/TIVA. Familiarity with tester‑interface optical techniques: Soft Defect Localization. Laser Voltage Probing. Frequency mapping. Time‑resolved emission. Experience with SEM nano‑probing (EBIC, EBAC, EBIRCH) on planar, SOI, or FinFET technologies. Knowledge of SCAN, Memory BIST, RF/Analog circuits. Understanding of reliability tests: CDM, HBM, TLP, HTOL, BHAST, Burn‑In, etc. Strong communication, organization, and project management skills. Ability to work in a laboratory environment. Willingness to work flexible hours, including weekend or night shifts. Experience with scripting/programming (Python, automation scripts, Power BI, etc.). Minimum Qualifications Bachelor’s degree in Electrical Engineering, Microelectronics, Physics, or related field. 0–2 years of hands‑on semiconductor failure analysis or physical/chemical lab experience. Preferred Qualifications Master’s degree in Electrical Engineering, Microelectronics, Physics, or related field. 2+ years experience in chip‑level failure analysis. Skills in: Automated Test Equipment (ATE). Data analysis. Product reliability and development

Hace 6 horas en Tijuana

Physical Verification Engineer (Semiconductors)

Minimum 2 years of experience in a hands-on PDK role. Expertise in Calibre/ICV/Pegasus runset coding for DRC/LVS/ERC/PERC/MPT/ESD/Latch-up/Antenna, etc. Experience with developing and customization of the StarRC/Calibre-xACT/QRC parasitic extraction flows. As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology. Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules (DRCs), etc., to meet design team requirements. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modifying existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other extraction tools. Utilizing your hands-on skills to revamp/rewrite and streamline the PEX flow. Understanding of Digital/Custom/Analog requirements for various post layout electrical flows. Develop custom extraction solutions for transistor level for design team requirements. Hands-on experience with Field solvers and RC reduction tools. Support design teams with solving their PEX challenges. Support the design teams with solving their PV challenges to facilitate the IP release and chip tapeouts. Collaborate with tool vendors and foundries for tools and flow improvements. Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design. Proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL. Good communication skills and ability to work collaboratively in a team environment. Educational Requirements Required: Bachelor's, Electrical Engineering (with Master’s preferred).

Hace 6 horas en Tijuana